The invention relates to methods of controlling frame memories, memory control circuits that control frame memories, and image processing apparatuses that incorporate the memory control circuits. Specifically, this invention relates to methods of controlling frame memories, memory control circuits, and image processing apparatuses with shortened delay periods before starting to output data read from the frame memories.
Image processing apparatuses, such as liquid crystal display apparatuses, which include memory control circuits for controlling frame memories are known. The image processing apparatuses perform image processing based on data that represent values of pixels constituting frames. In the image processing apparatuses, data representing values of pixels constituting a plurality of frames are received with an order of the frames. Data (current data) constituting a next ((N+1)-th) frame are received and written to the frame memory and, simultaneously, data (past data) constituting a previous (N-th) frame previously written to the frame memory are read from the frame memory. Processing (image processing) is performed by comparing the past data and the current data, and data that reflects the result of the processing is output.
An amount of data to be written to the frame memory is large. Accordingly, DRAM (Dynamic Random Access Memory) such as SDRAM (Synchronous Dynamic Random Access Memory), which is inexpensive and has a large memory capacity, is advantageously used as the frame memory. SDRAM has an address space defined by row and column addresses. SDRAM is a dynamic-type random access memory that requires refreshing within a predetermined interval.
When starting data access to SDRAM, specifying a row address and further specifying a column address when a predetermined period has lapsed after specifying the row address are required. Specifying the row and column addresses is required to be repeated each time after a predetermined amount of data has been accessed. In an image processing apparatus such as a liquid crystal display apparatus, on the other hand, it is necessary to continuously output the data. Accordingly, a memory control circuit constituting an image processing apparatus includes FIFOs (First-In First-Out memories) at the input-side and the output-side of SDRAM as shown in, for example, U.S. Pat. No. 7,023,413, which is hereby incorporated by reference in its entirety.
FIG. 8 shows an exemplary construction of a conventional memory control circuit.
The memory control circuit 100 shown in FIG. 8 includes Write FIFO 102, SDRAM controller 103, and Read FIFO 104. The memory control circuit 100 controls writing of data to and reading of data from the SDRAM 110. During a period of a line within a frame, reading of past data and writing of current data representing values of pixels constituting the line are performed under a control of the memory control circuit 100. In practice, during a first half of the period of the line, past data PD previously stored in SDRAM 110 are read and output through the Read FIFO 104. Further, in the second half of the period of the line, current data CD received through Write FIFO 102 is written to SDRAM 110. Further detailed explanation will be made with reference to FIG. 9.
FIG. 9 is a timing chart showing write and read access timings of the memory control circuit to SDRAM 1110 and to Write and Read FIFOs 102 and 104 shown in FIG. 8.
FIG. 9 shows waveforms of vertical synchronizing signal VSYNC, read data enable signal RDE, write data enable signal WDE. During each of the periods that the read data enable signal RDE and the write data enable signal WDE are in ‘H’ level, data of pixels of one of the lines constituting a frame is input to the memory control circuit 100. FIG. 9 also shows periods of reading the past data from SDRAM 110 and writing the read data to Read FIFO 104 (Past data read) and periods of reading the past data from Read FIFO 104 and outputting the read data from the memory control circuit 100 (Past data output). FIG. 9 further shows periods of inputting the current data into the memory control circuit 100 and writing the input data to Write FIFO 102 (Current data input), and periods of reading the current data from Write FIFO 102 and writing the read data to SDRAM 110 (Current data write).
At first, vertical synchronizing signal VSYNC that indicates a partition between the frames is input. Then, read data enable signal RDE changes from ‘L’ level to ‘H’ level. As a result, reading of past data PD, which are previously stored in SDRAM 110, starts. The past data PD read from SDRAM 110 is written to Read FIFO 104. Thereafter, the past data written to the FIFO is read and output from the memory control circuit. On the other hand, current data CD input to the memory control circuit are written to Write FIFO 102. Then, after the reading of past data from SDRAM 110 is completed, the current data CD is read from Write FIFO 102 and written to SDRAM 110.
As shown in FIG. 9, data constituting a line is input to the memory control circuit 100 during a period that read data enable signal RDE and write data enable signal WDE are in ‘H’ level. Past data PD are written to Read FIFO 104 during the first half of the period, and current data CD are read from Write FIFO 102 and written to SDRAM 110 during the second half of the same period. In truth, however, reading of current data CD from Write FIFO 102 and writing of the current data CD to SDRAM 110 are performed by also using a part of a horizontal blanking period after the changing of write data enable signal WDE to ‘L’ level.
The memory control circuit 100 shown in FIG. 8 starts reading of past data PD stored in SDRAM 110 after read data enable signal RDE changes from ‘L’ level to ‘H’ level. After read data enable signal RDE changes to ‘H’ level, however, there is a delay time, or latency, before starting to read past data PD. Accordingly, an image processing apparatus, which incorporates the memory control circuit 100 and performs processing (image processing) by comparing the current data and the past data, suffers from the following problems.
An image processing circuit in a liquid crystal display apparatus, which is an example of the image processing apparatus, performs image processing based on past data of a pixel at a certain position (or coordinates) in a previous frame and current data of the pixel at the same position in the next (or current) frame. The image processing is performed, for example, in order to improve the response speed of the liquid crystal display, and data reflecting the result of the processing is output.
In order to perform such a processing, the past data of a pixel and the current data of the same pixel are required to be input simultaneously. That is, a first delay period until the past data is read from the SDRAM 110 and input to the image processing circuit and a second delay period until the current data is input to the image processing circuit should be made equal with each other. Accordingly, an image processing apparatus generally includes a delay circuit, such as a shift register or a FIFO, to delay the current data during the period that the past data is read from the SDRAM. When the delay period for reading the past data is long, a larger shift register is required.
In general, the delay period for reading data from SDRAM is a sum of tRCD and CAS latency. Here, tRCD is a delay period between row address strobe signal and column address strobe signal measured by the number of clocks. CAS latency is a delay period between input of read command to output of read data measured by the number of clocks. In reality, it is difficult to directly input data to Read FIFO 104 after outputting the data from SDRAM 110 due to a difficulty in the timing adjustment. Accordingly, two or three stages of flip-flops are inserted between SDRAM and Read FIFO. As a result, start of output of the data from the memory control circuit 100 is further delayed.
For example, when an SDRAM with tRCD=3 and CAS latency=3 is used and two stages of flip-flops are inserted, 8 stages of flip-flops are needed to construct the shift-register. That is, when each of RGB values of a pixel is represented by 10-bit data, and two-channel parallel processing is performed, 8×10×2=160 flip-flops are needed for each of RGB values.
As explained above, a conventional memory control circuit 100 shown in FIG. 8 has a problem that a delay period from the start of inputting current data to the start of outputting past data stored in SDRAM 110 is long. Accordingly, in an image processing apparatus including the conventional memory control circuit 100, delaying the current data for a long period is required and, as a result, the size of the shift-register becomes large.